Non-volatile multi-time programmable (MTP) memories have been introduced for beneficial use in numerous applications where customization is required for both digital and analog designs. These applications include data encryption, reference trimming, manufacturing identification (ID), security ID, and many other applications. Some of the existing approaches to constructing MTP memories tend to suffer from long operation time (e.g., programming or erasing time) per cycle, smaller coupling ratio and/or large cell size. In addition, different voltage values may be required at various terminals to operate conventional MTP memories, leading to excessive terminal voltages. Incorporating MTP memories also typically comes at the expense of some additional processing steps.
Therefore, there is a need to provide a simplified MTP structure that has improved performance, and has a manufacturing process that is compatible with the standard complementary metal-oxide-semiconductor (CMOS) platform.